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system management ic with programmable quad voltage monitoring and supervisory functions ad5100 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 2 device-enabling outputs with 6 programmable monitoring inputs (see table 1 ) two 30 v monitoring inputs with shutdown control of external devices programmable overvoltage, undervoltage, turn-on and turn-off thresholds, and shutdown timings shutdown warning with fault detection reset control of external devices 5 v and 7.96 v monitoring inpu ts with reset control of external devices programmable reset thresholds and hold time emost-compatible inputs diagnostic application using v 2mon and v 4mon two supervisory functions watchdog reset controller with programmable timeout and selectable floating input manual reset control for external devices digital interface and programmability i 2 c-compatible interface otp 1 for permanent threshold and timing settings otp can be overwritten for dynamic adjustments power-up by edge triggered signal power-down over i 2 c bus operating range supply voltage: 6.0 v to 30 v temperature range: ?40c to +125c shutdown current: 5 a max operating current: 2 ma max high voltage input antimigration shielding pinouts applications automotive systems network equipment computers, controllers, and embedded systems 1 one-time programmable eprom with unlimited adjustment before otp execution. general description the ad5100 is a programmable system management ic that combines four channels of voltage monitoring and watchdog supervision. the ad5100 can be used to shut down external supplies, reset processors, or disable any other system electron- ics when the system malfunctions. the ad5100 can also be used to protect systems from improper device power-up sequencing. the ad5100, a robust watchdog reset controller, can monitor two 30 v inputs with shutdown and reset controls, one 2.3 v to 5.0 v input, and one 1.6 v to 7.96 v input. most monitoring input thresholds and timing settings can be programmed on-the-fly or permanently set with the otp memory feature. the ad5100 is versatile for system monitoring applications where critical microprocessor, dsp, and embedded systems operate under harsh conditions, such as automotive, industrial, or communications network environments. the ad5100 is available in a compact 16-lead qsop package and can operate in an extended automotive temperature range from ?40c to +125c. table 1. ad5100 general input and output information input monitoring range 1 shutdown control reset control fault detection v 1mon 6 v to 28.29 v yes yes yes v 2mon 3 v to 24.75 v yes yes yes v 3mon 2.32 v to 4.97 v no yes yes v 4mon 1.67 v to 7.96 v no yes yes wdi 0 v to 5 v yes yes no mr 0 v to 5 v no yes no 1 with programmable threshold and programmable delay.
ad5100 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? specifications ..................................................................................... 4 ? electrical specifications ............................................................... 4 ? timing specifications .................................................................. 7 ? absolute maximum ratings ............................................................ 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? one-time programmable (otp) options ............................. 10 ? theory of operation ...................................................................... 12 ? monitoring inputs .......................................................................... 13 ? v 1mon ............................................................................................ 13 ? v 2mon ............................................................................................ 14 ? v 3mon ............................................................................................ 15 ? v 4mon ............................................................................................ 16 ? watchdog input .......................................................................... 16 ? manual reset input .................................................................... 18 ? outputs ............................................................................................ 19 ? shutdown output, shdn ......................................................... 19 ? reset output, reset ................................................................. 19 ? shutdown warning, shdnwarn .......................................... 20 ? v 4out output ................................................................................ 20 ? power requirements ...................................................................... 21 ? internal power, v reg ................................................................... 21 ? v otp ............................................................................................... 21 ? protection .................................................................................... 22 ? ad5100 register map .................................................................... 23 ? i 2 c serial interface .......................................................................... 27 ? writing data to ad5100 ........................................................... 28 ? reading data from ad5100 ..................................................... 28 ? permanent setting of ad5100 registers (otp function) ... 29 ? temporary override of default settings ................................. 29 ? applications information .............................................................. 30 ? car battery and infotainment system supply monitoring ... 30 ? battery monitoring with fan control ..................................... 33 ? battery state of charge indicator and shutdown early warning monitoring .................................................................. 33 ? rising edge triggered wake-up mode ................................... 34 ? outline dimensions ....................................................................... 35 ? ordering guide .......................................................................... 35 ? revision history 9/08revision 0: initial version
ad5100 rev. 0 | page 3 of 36 05692-001 functional block diagram 55k ? 640k ? 130k ? 665k ? shutdown controller reset generator v 1mon (6v to 30v) v 4out reset shdnwarn shdn mr wdi detection and reset generator i 2 c controller otp fuse array register map fd register fault detection ad0 sda scl v otp wdi v 4mon (0.9v to 30v) v 3mon (2.5v to 5v) v 2mon (3v to 30v) ov/uv ad5100 on/off figure 1.
ad5100 rev. 0 | page 4 of 36 specifications electrical specifications 6 v v 1mon 30 v and 3 v v 2mon 30 v, ?40c t a +125c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit high voltage monitoring inputs v 1mon voltage range v 1mon 6 30 v input resistance r in_v1mon 36 55 70 k ov, uv threshold tolerance (see figure 7 and table 6 ) ov, uv t a = 25c ?1.6 +1.6 % t a = ?40c to +85c ?1.8 +1.8 % t a = ?40c to +125c ?2 +2 % hysteresis 1.5 % programmable shutdown hold time tolerance (see figure 7 and table 8 ) t 1sd_hold t a = 25c; does not apply to code 0x7 ?10 +10 % programmable shutdown delay tolerance (see figure 7 and table 8 ) t 1sd_delay t a = 25c; does not apply to code 0x7 ?10 +10 % t a = ?40c to +125c; does not apply to code 0x7 ?17 +17 % fault detection delay t fd_delay 60 s glitch immune time t glitch guaranteed by evaluation 45 s v 2mon input voltage v 2mon minimum voltage on v 2mon to ensure ad5100 v reg power-up 2.2 v voltage range 2 v 2mon 3 30 v input resistance r in_v2mon 500 640 760 k on, off threshold tolerance 3 (see figure 7 and table 6 ) on, off t a = 25c ?2 +2 % t a = ?40c to +85c ?2.4 +2.4 % t a = ?40c to +125c ?2.5 +2.5 % hysteresis 1.5 % turn-on programmable shdn hold time tolerance (see and ) figure 7 table 8 t 2sd_hold t a = 25c; does not apply to code 0x7 ?10 +10 % turn-off programmable shdn delay time tolerance (see and ) figure 7 table 8 t 2sd_delay t a = 25c; does not apply to code 0x07 ?10 +10 % t a = ?40c to +125c; does not apply to code 0x7 ?17 +17 % fault detection delay t fd_delay v 2mon_off only 60 s glitch immune time t glitch 45 s shdn shdn output high v oh v rail = v reg , i source = 40 a 2.4 v v rail = v 1mon , i source = 600 a v 1mon ? 0.5 v shdn output low v ol i sink = 1.6 ma 0.4 v v 1mon = 12 v, i sink = 40 ma 1.5 3 v shdn sink current i sink v 1mon = 12 v, shdn forced to 12 v 10 13.5 ma shdnwarn (open-drain output) shdnwarn inactive leakage current i oh_shdnwarn 0.9 a shdnwarn active v ol_shdnwarn i sink = 3 ma 0.4 v
ad5100 rev. 0 | page 5 of 36 parameter symbol conditions min typ 1 max unit low voltage monitoring inputs v 3mon , v 4mon v 3mon voltage range v 3mon 2.0 5.5 v input resistance r in_v3mon 110 130 155 k v 3mon threshold tolerance (see figure 10 and table 6 ) v 3mon t a = 25c ?2.5 +2.5 % t a = ?40c to +85c ?2.75 +2.75 % t a = ?40c to +125c ?3 +3 % v 3mon hysteresis v 3_hysteresis 1.2 % v 4mon voltage range 4 v 4mon 0.9 30 v input resistance r in_v4mon 580 665 775 k v 4mon threshold tolerance (see figure 12 and table 6 ) v 4mon t a = 25c ?2.5 +2.5 % t a = ?40c to +85c ?2.75 +2.75 % t a = ?40c to +125c ?3 +3 % v 4mon hysteresis v 4_hysteresis 5 % reset reset hold time tolerance (see , , and ) figure 10 figure 12 table 8 t rs_hold t a = 25c; does not apply to code 0x6 and code 0x7 ?10 +10 % t a = ?40c to +125c; does not apply to code 0x6 and code 0x7 ?17 +17 % v 3mon /v 4mon -to- reset delay t rs_delay 60 s reset output voltage high v oh v 3mon 4.38 v, i source = 120 a v 3mon ? 1.5 v 2.7 v < v 3mon 4.38 v, i source = 30 a 0.8 v 3mon v 2.3 v < v 3mon 2.7 v, i source = 20 a 0.8 v 3mon v 1.8 v v 3mon 2.3 v, i source = 8 a 0.8 v 3mon v reset output voltage low v ol v 3mon > 4.38 v, i sink = 3.2 ma 0.4 v v 3mon < 4.38 v, i sink = 1.2 ma 0.3 v reset output short-circuit current 5 i source reset = 0, v 3mon = 5.5 v 825 a reset = 0, v 3mon = 3.6 v 400 a glitch immune time t glitch 50 s v 4out maximum output v 4out_max open drain 5.5 v v 4out propagation delay t v4out_delay 70 s v 4out maximum frequency f v4out applies to reset disabled only 10 khz wdi (watchdog input) wdi programmable timeout tolerance (see figure 13 and table 8 ) t wd t a = 25c ?10 +10 % t a = ?40c to +125c ?17 +17 % wdi pulse width t wdi 50 ns watchdog initiated reset pulse width t wdr when no wdi t wd /50 ms watchdog initiated shdn t wd_shdn when no wdi activity > 4 t wd 1 sec wdi input voltage low v il_wd 0.3 v 3mon v wdi input voltage high v ih_wd 0.7 v 3mon v wdi input current wdi = v 3mon 160 a wdi = 0 ?20 a
ad5100 rev. 0 | page 6 of 36 parameter symbol conditions min typ 1 max unit mr (manual reset) input mr input voltage low v il_mr 0.3 v 3mon v mr input voltage high v ih_mr 0.7 v 3mon v input current 1 a mr pulse width t mr 1 s mr deglitching t mr_glitch 100 ns mr -to- reset delay t mr_delay 1 s mr pull-up resistance (internal to v 3mon ) 50 60 75 k reset hold time tolerance (see and ) figure 12 table 8 t rs_hold t a = 25c; does not apply to code 0x6 and code 0x7 ?10 +10 % t a = ?40c to +125c; does not apply to code 0x06 and code 0x7 ?17 +17 % serial interfaces input logic high (scl, sda) 6 v ih external r pull-up = 2.2 k 2.0 5.5 v input logic low (scl, sda) v il external r pull-up = 2.2 k 0 0.8 v output logic high (sda) v oh v rail = 2 v to 5.5 v 0.7 v rail v output logic low (sda) v ol i ol = 3 ma 0 0.4 v input current v in = 0 v to 5.5 v 1 a input capacitance c i 5 pf power supply supply voltage range v 1mon 6.0 30 v sleep mode supply current i sleep_v1mon v 2mon = 0 v 5 a active mode supply current i power_v1mon v 2mon = 12 v 2 ma v 2mon edge triggered mode selected 2 ma device power-on threshold v 2mon, ih 2.2 v v 2mon, il 0.4 v device power-up v 2mon , minimum pulse width t v2mon_pw 4 ms device power-down delay t vreg_off_delay v 2mon < 0.4 v (normal mode) 2 sec i 2 c-initiated power-down 10 s otp supply voltage 7 v otp for otp only 5.5 v otp supply current 8 i votp for otp only 84 ma otp settling time 9 t s_otp 12 ms 1 represent typical values at 25c, v 1mon = 12 v, and v 2mon = 12 v. 2 initial v 2mon turn-on minimum remains as 2.2 v but the 3 v to 30 v specif ications apply afterward. 3 does not apply if v 2mon is a digital signal. 4 v 4mon threshold limits (see table 6) are designed to primarily allow v 4mon to monitor low voltage inputs. the v 4mon input pin is capable of withstanding voltages up to 30 v. one application where this 30 v capability is useful is electronic media-oriented systems transport (emost) diagnostic ci rcuits. 5 the reset short-circuit current is the maximum pull-up current when reset is driven low by a microproc essor bidirectional reset pin. 6 it is typical for the scl and sda to have resistors pulled up to v 3mon . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull-up resistors. 7 v otp can be furnished by an external 5.5 v power supply, rather than an on-board power supply, when performin g factory programming. a 10 f tantalum capacitor is required on v otp during operation regardless of wh ether the otp fuse s are programmed. 8 the otp supply source must be capable of supplying a minimum of 100 ma becaus e some ad5100 parts requir e a current slightly gr eater than the typical value of 84 ma. 9 the otp settling time occurs only once if the otp function is used.
ad5100 rev. 0 | page 7 of 36 timing specifications table 3. parameter description min typ max unit i 2 c interface timing characteristics 1 , 2 f scl scl clock frequency 400 khz t 1 t buf , bus free time between start and stop 1.3 s t 2 t hd;sta , hold time after (repeated) start condition; after this period, the first clock is generated 0.6 s t 3 t low , low period of scl clock 1.3 s t 4 t high , high period of scl clock 0.6 50 s t 5 t su;sta , setup time for start condition 0.6 s t 6 t hd;dat , data hold time 0.9 s t 7 t su;dat , data setup time 0.1 s t 8 t f , fall time of both sda and scl signals 0.3 s t 9 t r , rise time of both sda and scl signals 0.3 s t 10 t su;sto , setup time for stop condition 0.6 s 1 guaranteed by design and not subject to production test. 2 see figure 2. scl t 2 t 3 t 4 t 7 t 5 t 10 t 2 t 8 t 1 ps sp t 9 t 6 t 8 s d a 05692-002 t 9 figure 2. digital interface timing diagram
ad5100 rev. 0 | page 8 of 36 absolute maximum ratings table 4. parameter rating v 1mon to gnd ?0.3 v, +33 v v 2mon to gnd ?0.3 v, +33 v v 3mon to gnd ?0.3 v, +7 v v 4mon to gnd ?0.3 v, +33 v v otp to gnd ?0.3 v, +7 v digital input voltage to gnd ( mr , wdi, scl, sda, ad0) 0 v, +7 v digital output voltage to gnd ( reset , v 4out , shdnwarn ) 0 v, +7 v digital output voltage to gnd ( shdn ) 0 v, +33 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c esd rating (hbm) 3.5 kv maximum junction temperature (t jmax ) 150c power dissipation 1 (t jmax ? t a 2 )/ ja thermal impedance 3 ja junction-to-ambient 105.44c/w jc junction-to-case 38.8c/w ir reflow soldering (rohs-compliant package) peak temperature 260c (+0c) time at peak temperature 20 sec to 40 sec ramp-up rate 3c/sec max ramp-down rate ?6c/sec max time from 25c to peak temperature 8 minutes max 1 values relate to the package being used on a 4-layer board. 2 t a = ambient temperature. 3 junction-to-case resistance is applicable to components featuring a preferential flow direction, for example, components mounted on a heat sink. junction-to-ambient resistan ce is more useful for air-cooled pcb-mounted components. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5100 rev. 0 | page 9 of 36 05692-003 pin configuration and fu nction descriptions v 1mon 1 gnd 2 nc = no connect v otp 3 v 3mon 4 v 2mon 16 gnd/nc 15 v 4mon 14 mr 5 ad0 13 wdi 6 shdn 12 scl 7 shdnwarn 11 v 4out 10 sda 8 reset 9 ad5100 top view (not to scale) figure 3. pin configuration table 5. ad5100 pin function descriptions pin o. mnemonic description 1 v 1mon high voltage monitoring input. ad5100 internal supply is derived from v 1mon . there must be a 10 f electrolytic capacitor between this pin and gnd, placed as close as possible to the v 1mon pin. 2 gnd ground. 3 v otp one-time programmable supply voltage for eprom. a 10 f decoupling capacitor (low esr) to gnd is required when not fuse programming. 4 v 3mon low voltage monitoring input. 5 mr manual reset input. active low. 6 wdi watchdog input. 7 scl i 2 c serial input register clock. open-drain input. if it is driven directly from a logic driver without the pull-up resistor, ensure that the v ih minimum is 3.3 v. 8 sda i 2 c serial data input/output. op en-drain input/output. if it is driven directly from a logic driver without the pull- up resistor, ensure that the v ih minimum is 3.3 v. 9 reset reset. push-pull output with rail voltage of v 3mon . 10 v 4out open-drain output. triggered by v 4mon . 11 shdnwarn shutdown warning. active low, open-drain output. 12 shdn shutdown output. push-pull output with selectable rail voltage of v 1mon or v reg , the ad5100 internal power (30 v maximum). 13 ad0 i 2 c slave address configuration. if tied high, th is pin can only be tied to 3.3 v maximum. 14 v 4mon low voltage monitoring input. capable of withstanding 30 v. 15 gnd/nc ground/no connect. can be grounded or left floating but do not connect to any other potentials. 16 v 2mon high voltage monitoring input. it is also the internal supply voltage enabling input. 05692-00 4 1 2 3 4 16 15 14 5 13 6 12 7 11 10 8 9 ad5100 top view (not to scale) gnd figure 4. recommended pcb layout for shielded high voltage inputs
ad5100 rev. 0 | page 10 of 36 one-time programmable (otp) options all values are typical ratings; see table 2 for tolerances. table 6. available programmable thresholds at t a = 25c v 1mon ov threshold v 1mon uv threshold v 2mon on threshold v 2mon off threshold v 3mon threshold v 4mon threshold 7.92 v 6.00 v 3.00 v 3.00 v 2.32 v 1.67 v 9.00 v 6.49 v 3.5 v 3.5 v 2.64 v 2.31 v 9.90 v 6.95 v 4.00 v 4.00 v 2.93 v 1 3.05 v 11.00 v 7.47 v 4.77 v 4.77 v 3.10 v 4.62 v 12.00 v 7.92 v 6.00 v 6.00 v 4.36 v 6.51 v 13.20 v 8.43 v 1 6.49 v 6.49 v 4.65 v 7.16 v 14.14 v 9.00 v 6.95 v 6.95 v 1 4.75 v 7.54 v 1 15.23 v 9.43 v 7.47 v 1 7.47 v 4.97 v 7.96 v 15.84 v 9.90 v 7.92 v 7.92 v reserved reserved 17.22 v 10.42 v 8.43 v 8.43 v reserved reserved 18.00 v 1 11.00 v 9.00 v 9.00 v reserved reserved 18.86 v 11.65 v 9.43 v 9.43 v reserved reserved 19.80 v 12.00 v 9.90 v 9.90 v reserved reserved 22.00 v 12.38 v 15.23 v 15.23 v reserved reserved 24.75 v 13.20 v 19.80 v 19.80 v reserved reserved 28.29 v 13.66 v 24.75 v rising edge triggered wake-up mode reserved reserved 1 default. v 1mon_ov must be > v 1mon_uv . v 2mon_off is ignored if > v 2mon_on but v 2mon_off cannot be = v 2mon_on . table 7. look-up table of programming code vs. typical thresholds shown in table 6 code v 1mon ov threshold v 1mon uv threshold v 2mon on threshold v 2mon off threshold v 3mon threshold v 4mon threshold 0000 18.00 v 1 8.43 v 1 7.47 v 1 6.95 v 1 2.93 v 1 7.54 v 1 0001 18.86 v 7.92 v 6.95 v 7.47 v 4.65 v 1.67 v 0010 15.84 v 9.43 v 6.49 v 6.00 v 4.75 v 2.31 v 0011 17.22 v 9.00 v 6.00 v 6.49 v 4.97 v 3.05 v 0100 24.75 v 6.49 v 4.77 v 4.00 v 2.32 v 4.62 v 0101 28.29 v 6.00 v 4.00 v 4.77 v 2.64 v 6.51 v 0110 19.80 v 7.47 v 3.50 v 3.00 v 4.36 v 7.16 v 0111 22.00 v 6.95 v 3.00 v 3.50 v 3.10 v 7.96 v 1000 9.90 v 12.38 v 24.75 v 19.80 v reserved reserved 1001 11.00 v 12.00 v 19.80 v rising edge triggered wake-up mode reserved reserved 1010 7.92 v 13.66 v 15.23 v 9.90 v reserved reserved 1011 9.00 v 13.20 v 9.90 v 15.23 v reserved reserved 1100 14.14 v 10.42 v 9.43 v 9.00 v reserved reserved 1101 15.23 v 9.90 v 9.00 v 9.43 v reserved reserved 1110 12.00 v 11.65 v 8.43 v 7.92 v reserved reserved 1111 13.20 v 11.00 v 7.92 v 8.43 v reserved reserved 1 default.
ad5100 rev. 0 | page 11 of 36 table 8. available programmable hold time and delay t 1sd_hold t 1sd_delay t 2sd_hold t 2sd_delay t rs_hold t wd 0.07 ms 0.07 ms 0.07 ms 0.07 ms 0.1 ms 100 ms 20 ms 50 ms 10 ms 1 50 ms 1 ms 250 ms 40 ms 100 ms 20 ms 100 ms 1 15 ms 500 ms 60 ms 200 ms 30 ms 200 ms 30 ms 750 ms 80 ms 400 ms 40 ms 400 ms 50 ms 1000 ms 100 ms 800 ms 50 ms 800 ms 100 ms 1250 ms 150 ms 1000 ms 100 ms 1000 ms 150 ms 1500 ms 1 200 ms 1 1200 ms 1 200 ms 1200 ms 200 ms 1 2000 ms 1 default. table 9. look-up table of programming code vs. typical timings shown in table 8 code t 1sd_hold t 1sd_delay t 2sd_hold t 2sd_delay t rs_hold t wd 000 200 ms 1 1200 ms 1 10 ms 1 100 ms 1 200 ms 1 1500 ms 1 001 150 ms 1000 ms 20 ms 50 ms 150 ms 2000 ms 010 100 ms 800 ms 30 ms 200 ms 100 ms 1250 ms 011 80 ms 400 ms 40 ms 400 ms 50 ms 1000 ms 100 60 ms 200 ms 50 ms 800 ms 30 ms 750 ms 101 40 ms 100 ms 100 ms 1000 ms 15 ms 500 ms 110 20 ms 50 ms 200 ms 1200 ms 1 ms 250 ms 111 0.07 ms 0.07 ms 0.07 ms 0.07 ms 0.1 ms 100 ms 1 default.
ad5100 rev. 0 | page 12 of 36 theory of operation the ad5100 is a programmable system management ic that has four channels of monitoring inputs. three inputs have high voltage (30 v) capability. for example, if the ad5100 is used in an automotive application, v 1mon (monitoring input 1) can be connected to the battery and the v 2mon can be connected to the ignition switch, a rising edge trigger wake-up signal, or the media-oriented systems transport (most) wake-up signal (v 4mon is connected to v 2mon for most applications). two other inputs, v 3mon and v 4mon , are designed for low voltage monitoring, with programmable thresholds from 2.93 v to 7.96 v. the two high voltage monitoring inputs control the shutdown signal, shdn and reset signal, reset , while the two low voltage monitoring inputs control the reset signal, reset . shdn and reset are both disabling signals for external devices. the differences between these two outputs are in output level and driving capabilities, as described in the section. the wdi (watchdog) and outputs mr (manual reset) inputs also control the reset output, for use with an external digital processor. shows the general flow chart and summarizes the ad5100 functions and features. figure 5 table 10 05692-005 yes no shdn = 0* shdn = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 yes no shdn = 0* v 1mon > uv v 1mon < ov yes yes no shdn = 0 no shdn = 0 shdn = 1 v 2mon > on v 2mon > off (v 2mon rising edge sensitive selected) v 2mon level sensitive selected yes no continue monitoring no yes v 4mon > threshold v 4out = 0 v 4out = 1 no yes using v 4out for pwm no yes v 4mon > threshold no yes v 3mon > threshold yes no valid wdi yes no valid wdi no yes floating wdi disabled yes standard wdi selected yes no mr = 1 reset = 0 yes no floating wdi no (advance wdi selected) * see table 11 reset configuration register: if [0] = 0, then shdn = 0 and reset = 0 if [0] = 1, then shdn = 0 and reset = 1 default paths figure 5. general flow chart table 10. ad5100 functions and features input monitoring range shutdown control reset control fault detection functions and features if ot used v 1mon 6 v to 28.29 v yes yes yes overvoltage/undervoltage thresholds does not apply v 2mon 3 v to 24.75 v yes yes yes on/off voltage thresholds; pseudo rising edge triggered, wake-up selectable; most wake-up signal (v 2mon connected to v 4mon ) connect to v 1mon , minimum input 6 v v 3mon 2.32 v to 4.97 v no yes yes connect to v otp and set threshold to minimum v 4mon 1.67 v to 7.96 v no yes yes additional output connect to gnd wdi 0 v to 5 v yes yes no standard, advance, or floating; watchdog selectable leave floating mr 0 v to 5 v yes yes no highest priority on reset over other inputs leave floating
ad5100 rev. 0 | page 13 of 36 monitoring inputs v 1mon v 1mon is a high voltage monitoring input that controls the shdn and reset functions of the external devices. in addition, it provides a shutdown warning to the system. v 1mon monitors inputs from 6 v to 30 v. the v 1mon pin is monitored by two comparators, one for overvol- tage and one for undervoltage detection. both are designed with 1.5% hysteresis. when the v 1mon input goes above the programmed overvoltage (ov) threshold, the comparator becomes active immediately, indicating that an ov condition has occurred. due to hysteresis, the v 1mon input must be brought below the programmed ov threshold by 1.5% before the comparator becomes inactive, indicating that the ov condition has gone away (see figure 6 ). 0 5692-007 v 1mon v 1mon_uv ov comparator active ov comparator inactive uv comparator active uv comparator inactive v 1mon_ov hysteresis hysteresis figure 6. v 1mon hysteresis when the v 1mon input drops below the programmed under- voltage (uv) threshold, the comparator becomes active immediately, indicating that a uv condition has occurred. similarly, due to hysteresis, the v 1mon input must be brought above the programmed uv threshold by 1.5% before the comparator becomes inactive, indicating that the uv condition has gone away. both v 1mon comparators are used (in conjunction with hold and delay timers) to control the shdn and reset pins. v 1mon has a 16-level programmable ov threshold (register 0x01) and uv threshold (register 0x02) with an 8-step 0.07 ms to 200 ms shutdown hold time (t 1sd_hold ) and 0.07 ms to 1200 ms shutdown delay (t 1sd_delay ). the shutdown hold time means that the shdn signal is held low for t 1sd_hold after v 1mon returns within its uv and ov thresholds. the shutdown delay means that the shdn signal activation is delayed until the programmed t 1sd_delay has elapsed. shdn activates once the voltage on v 1mon is outside the ov or uv threshold for a time longer than t glitch . reset follows shdn delay and hold timings when triggered by v imon . the ov threshold chosen must be greater than the uv threshold. when the shutdown is triggered, either because the input has reached the ov or uv threshold, such fault conditions are temporarily recorded in the fault detection register. the shdnwarn output transitions low for signaling before the shutdown output, shdn , activates. the timing of the shdn output is dependent on how long the shutdown- programmed delay (t 1sd_delay ) is set relative to the shdnwarn propagation delay (t fd_delay ). this feature attempts to allow the system to finish any critical housekeeping tasks before shutting down the external device. the v 1mon , shutdown, and shutdown warning timing diagrams are shown in figure 7 . the ranges of ov and uv thresholds are shown in table 6 , and the programming codes for the selected thresholds are found in table 7 . the defaulted ov threshold is 18.00 v and, for uv threshold, it is 8.43 v. similarly, the ranges of shutdown hold and delay times are shown in table 8 , and the programming codes for the selected timings are shown in table 9 . the default shutdown hold time is 200 ms; for shutdown delay time, it is 1200 ms. v 1mon exhibits typical input resistance of 55 k that users should take into account for loading effect. the voltage at v 1mon provides the power for the ad5100, but a valid signal on v 2mon must be present before the internal power rail, v reg , starts operation. details are explained in the power requirements section.
ad5100 rev. 0 | page 14 of 36 05692-006 v 1mon v 2mon v 1mon_ov* v 1mon_uv* v 2mon_off* v 2mon_on* t 2sd_hold* t fd_delay t fd_delay t fd_delay shdnwarn shdn and reset notes 1. * = programmable. 2. # = the duration of the t min must be shorter than t vreg_off_delay or else the ad5100 will be powered off. t glitch t glitch t 2sd_hold* t 1sd_hold* t 1sd_hold* t 1sd_delay* t 1sd_delay* t fd_delay t 2sd_delay* t min # t 2sd_delay* figure 7. v 1mon and v 2mon shutdown timing diagrams in level-sensitive mode (note that reset follows shdn ) v 2mon v 2mon is a high voltage monitoring input that controls the shdn and reset functions of the external devices. v 2mon monitors inputs from 3 v to 30 v. it has a 16-level programmable turn-on and turn-off (on, off) hysteresis thresholds (register 0x03 and register 0x04), with an 8-step 0.07 ms to 200 ms shutdown hold time (t 2sd_hold ) and 0.07 ms to 1200 ms shutdown delay (t 2sd_delay ). the v 2mon pin is monitored by two comparators, one for turn- on and one for turn-off detection, in the level-sensitive power- up mode. both are designed with 1.5% hysteresis. only the turn-on monitoring comparator is used if the rising edge triggered wake-up mode is selected. when the v 2mon input goes above the programmed v 2mon on threshold, the comparator becomes active immediately, indicat- ing that an on condition has occurred. due to hysteresis, the v 2mon input must be brought below the programmed threshold by 1.5% before the comparator becomes inactive, indicating that the on condition has gone away (see figure 8 ). when the v 2mon input drops below the programmed threshold, the comparator becomes active immediately, indicating that a v 2mon off condition has occurred. similarly, due to hysteresis, the v 2mon input must be brought above the programmed threshold by 1.5% before the comparator becomes inactive, indicating that the off condition has gone away. 0 5692-008 v 2mon v 2mon_off on comparator active on comparator inactive off comparator active off comparator inactive v 2mon_on hysteresis hysteresis figure 8. v 2mon hysteresis by default, v 2mon is level sensitive and the on and off thresholds are both monitored. the on threshold chosen must be greater than the off threshold. when the shdn output is activated by the input reaching the v 2mon_off threshold, such fault condition is temporarily recorded in the fault detection register. the shdnwarn output transitions low for signaling before the shutdown output, shdn , activates. the timing of the shdn output is dependent on how long the shutdown programmed delay (t 2sd_delay ) is set relative to the shdnwarn propagation delay (t fd_delay ). this feature allows the system to finish any critical housekeeping tasks before shutting down the external device. shdn activates once the voltage on v 2mon is outside the threshold for a time longer than t glitch . reset follows shdn delay and hold timings when triggered by v 2mon . the v 2mon , shutdown, and shutdown warning timing diagrams are shown in figure 7 .
ad5100 rev. 0 | page 15 of 36 for the selected-thresholds are found in d and the off threshold t a reg eta ke into account for loading effect. controls the reset the ranges of on and off thresholds are shown in table 6 and the programming codes table 7 . the default on threshold is 7.47 v and off threshold is 6.95 v. similarly, the ranges of shutdown hold and delay times are shown in table 8 , and the programming codes of the selected timings are found in table 9 . the default shutdown hold time is 10 ms and the delay time is 100 ms. v 2mon_off is ignored if v 2mon_off is greater than v 2mon_on but v 2mon_off cannot equal v 2mon_on. if v 2mon is selected with rising edge triggered wake-up mode, only the on threshold is monitore is ignored. v 2mon is put into rising edge triggered mode by setting v 2mon off threshold, register 0x04[3:0] to 1001 the voltage at v 1mon provides the power for the ad5100, bu valid signal on v 2mon must be present before the internal v starts operating. d ils are explained in the power requirements section. v 2mon exhibits typical input resistance of 640 k that users should ta v 3mon v 3mon is a low voltage monitoring input that of an external device. gned with 1.5% hysteresis. uv function the v 3mon pin is monitored by a comparator to detect an undervoltage condition. it is desi when the v 3mon input drops below the programmed uv threshold, the comparator becomes active immediately, indicating that a uv condition has occurred. due to hysteresis, the v 3mon input must be brought above the programmed threshold by 1.5% before the comparator becomes inactive, indicating that the uv condition has gone away (see figure 9 ). 05692-010 v 3mon v 3mon_uv hysteresis uv comparator inactive uv comparator inactive figure 9. v 3mon hysteresis the v 3mon comparator is used (in conjunction with a hold timer) to control the reset pin. v 3mon monitors inputs from 2.0 v to 5.5 v. it has an 8-step programmable reset threshold (re gister 0x05) with an 8-step me 0.1 ms to 200 ms reset hold time (t rs_hold ). the reset hold ti means that the reset output remains activate when v 3mon go above its uv threshold, until t rs_hold has elapsed. this allows the reset of an external device to be held until the programmed time is reached. the v 3mon and es reset timing diagrams are shown in figure 10 . the range of thres holds is shown in table 6 and the programming code for the selected threshold is found in tabl e 7 . the default monitoring threshold is 2.93 v. the range of reset hold times is shown in tabl e 8 and the programming code of the selected timing is found in table 9 . the default reset hold time is 200 ms. v 3mon exhibits typical input resistance of 130 k that users should ta ke into account for loading effect. the mr input has an internal resistor pull-up tov 3mon . the reset output is push-pull, between v 3mon and gnd. 05692-009 v 3mon v 3mon t glitch reset notes 1. * = programmable t rs_hold* t rs_delay t rs_hold* t rs_delay figure 10. v 3mon , reset timing diagrams
ad5100 rev. 0 | page 16 of 36 v 4mon v 4mon is a low voltage monitoring input that controls the reset function of an external device or provides a comparator output, v 4out . the v 4mon pin is monitored by a comparator to detect an undervoltage condition. it is designed with 5% hysteresis. when the v 4mon input drops below the programmed uv thresh- old, the comparator becomes active immediately, indicating that a uv condition has occurred. due to hysteresis, the v 4mon input must be brought above the programmed uv threshold by 5% before the comparator becomes inactive, indicating that the uv condition has gone away (see figure 11 ). 0 5692-012 v 4mon v 4mon_uv uv comparator inactive uv comparator inactive hysteresis figure 11. v 4mon hysteresis the v 4mon comparator is used to control the v 4out pin and (in conjunction with a hold timer) to control the reset pin. to configure v 4mon to control the reset pin, set register 0x0d[3] to 0. setting this bit to 1 prevents v 4mon from causing reset to activate. v 4mon input voltage range is up to 30 v. it has an 8-step programmable reset threshold (register 0x06) from 1.67 v to 7.96 v, with an 8-step 0.1 ms to 200 ms reset hold time (t rs_hold ). the v 4mon , reset , and v 4out timing diagrams are shown in . the range of thresholds is shown in , and the programming code for the selected threshold is found in . the default monitoring threshold is 7.54 v. similarly, the range of reset hold time is shown in , and the programming code of the selected timing is found in . figure 12 table 6 table 8 table 8 table 9 v 4mon exhibits typical input resistance of 665 k that users should take into account for loading effect. watchdog input the watchdog input (wdi) circuit attempts to reset the system to a known good state if a software or hardware glitch renders the system processor inactive for a duration that is longer than the timeout period. the timeout period, t wd , is programmable in eight steps from 100 ms to 2000 ms. the watchdog circuit is independent of any cpu clock that the watchdog is monitoring. the range of watchdog timeout is shown in tabl e 8 , and the programming code of the selected timeout is found in table 9 . the default timeout is 1500 ms. the watchdog is disabled during power-up. wdi starts monitor- ing once reset is high. the ad5100 provides a standard or advanced watchdog monitoring function. register 0x0f[3] sets the watchdog function to either standard or advanced mode. ? register 0x0f[3] = 0: standard watchdog mode ? register 0x0f[3[ = 1: advanced watchdog mode v 4mon v 4mon v 4out t glitch reset notes 1. * = programmable. 2. most applications using v 4out require disabling of v 4mon triggered reset. 05692-011 t rs_hold* t rs_hold* t rs_delay t rs_delay figure 12. v 4mon , reset , and v 4out timing diagrams
ad5100 rev. 0 | page 17 of 36 standard watchdog mode in the default standard watchdog mode, if wdi remains either high or low for longer than the timeout period, t wd , a reset pulse is generated in an attempt to allow the system processor to re-establish the wdi signal. the reset pulses continue indefi- nitely until a valid watchdog signal, a rising or falling edge signal at the wdi, is received. the internal watchdog timer clears whenever a reset is asserted. the standard wdi and reset timing diagrams are shown in . figure 13 advanced watchdog mode the ad5100 can be programmed into an advanced watchdog mode. in this mode, if wdi remains either high or low for longer than the timeout period, t wd , a reset pulse is generated, as per standard mode. however, if the wdi input remains inactive after three such reset pulses, concurrent with the fourth reset pulse, shdn is also asserted. shdn is released after 1 second. these actions repeat indefinitely (unless action is taken by the user), if the processor is not responding. the advanced wdi and reset timing diagrams are shown in . figure 14 0 5692-013 t wdi t wd t wdr t wd t wdr wdi reset pulse continuous pulses until watchdog awakes reset t wdr = watchdog-initiated reset pulse width t wdi = watchdog pulse width t wd = watchdog programmable time figure 13. standard watchdogpulsing reset until watchdog awakes 05692-014 t wdi t wd t wdi t wd_shdn t wd t wdr 3 reset pulses 1 reset pulse shutdown at 4th reset pulse release after 1s wdi reset shdn figure 14. advanced watchdog shdn asserted after three trials of resetting the watchdog ( shdn released after 1 second and the cycle repeats)
ad5100 rev. 0 | page 18 of 36 floating wdi input if the wdi pin is floating, the watchdog function is disabled by default. however, floating watchdog can be enabled in the reset configuration register such that a broken wdi connection or any unusual condition that makes wdi float triggers the reset. ? register 0x0d[3] = 0: floating wdi input activates reset ? register 0x0d[3] = 1: floating wdi input does not activate reset enabling or disabling the floating wdi feature can be changed dynamically, provided that the otp fuse of the reset configura- tion register is not blown or that the otp overridden function is selected. manual reset input manual reset ( mr ) is an active low input to the ad5100 and has an internal pull-up resistor to v 3mon . if the input signal on the mr pin goes low, reset is activated. mr can be driven from a cmos logic signal. the mr and reset timing diagrams are shown in . note that figure 15 reset is activated after t mr_delay and is held for t rs_hold after the mr signal has gone high again. mr has the highest priority in triggering the reset over any other monitoring inputs. 05692-015 t mr t mr_delay < t mr_glitch t rs_hold* mr * = programmable reset figure 15. manual reset ( mr ) timing diagram
ad5100 rev. 0 | page 19 of 36 outputs shutdown output, shdn the shutdown output, shdn , is triggered by v 1mon or v 2mon over- or underthreshold values, or as the result of a failed watchdog input. shdn can also be asserted low at any time by writing to certain registers on the ad5100. the shutdown generator asserts a logic low shdn signal based on the following conditions: ? during power-up ? when v 1mon goes over or under the threshold (see figure 7 ) ? when v 2mon is below the turn-on threshold during the rising edge or the turn-off threshold during the falling edge in level-sensitive mode (see figure 7 ) ? when the external monitoring processor cannot issue the necessary wdi signal and advanced wdi mode is selected (see figure 10 and figure 9 ) ? i 2 c? programmed shutdown to a c t iv ate shdn by writing to the part, the user must first enable this feature by writing to register 0x18[4]. ? register 0x18[4] = 0: enable software control of shdn ? register 0x18[4] = 1: disable software control of shdn once the feature is enabled, control of shdn is achieved by writing to register 0x16[2]. ? register 0x16[2] = 0: shdn output not controlled by software ? register 0x16[2] = 1: shdn output is pulled low the shdn signal is released after the programmable hold time, t sd_hold . the shdn output is push-pull configured with an i 2 c- selectable rail voltage of either v 1mon in default or internal v reg . register 0x0e controls the voltage rail for shdn . ? register 0x0e[3] = 0: shdn uses v 1mon rail ? register 0x0e[3] =1: shdn uses v reg rail figure 16 shows the shdn output configuration. pull-down resistor r1 ensures that shdn is pulled to ground when the ad5100 is not powered. when ad5100 is powered, m2a and m2b are both on. m2a has relatively lower impedance than m2b and r1 so the shdn remains low at shutdown. when the ad5100 settles, sw1 is turned on. m1 is stronger than m2a so shdn is pulled to the rail, which takes ad5100 out of the shutdown mode. in some applications, the ad5100 may monitor and control power regulators where the input and enable pins are next to each other in a fine pitch. this may pose reliability concerns under some abnormal conditions. to prevent errors from happen- ing, the ad5100 shutdown output features smart-load detection to ensure that the shutdown responds. for example, if the car battery has not started for a long time, a resistive dendrite may have formed across the shdn pin and the battery terminal (v 1mon ). the dendrite is blown immediately because m2a is designed with adequate current sinking capability and remains in the on position to offer such protection. in another situation, if the shdn pin is hard-shorted to the 12 v battery, the short- circuit detector opens sw2 and limits the current by the high impedance m2b. 05692-016 v 1mon m1 m2a m2b sw3 sw1 sw2 low-z high-z m3 r1 shdn # # * v reg level shifter short-circuit detect * notes 1. # = i 2 c selectable 2. * = default figure 16. shutdown output reset output, reset the reset output, reset , is triggered by v 3mon or v 4mon underthreshold values. reset activation can also be the result of the processor not generating the proper watchdog signal, if mr input is triggered, or if shdn is activated. the reset generator asserts the reset signal based on the following conditions: ? during power-up ? when v 3mon drops below the threshold (see figure 10 ) ? when v 4mon drops below the threshold (see figure 12 ) ? when shdn output is asserted (see and ); figure 7 figure 14 reset follows shdn hold and delay timings if triggered by the shdn output ? when the external monitoring processor cannot issue the necessary wdi signal (see figure 13 and figure 14 ) ? when mr is asserted (see ) figure 15 reset is active low by default, but can be configured for active high operation. register 0x0d[1] controls the activation polarity of reset . ? register 0x0d[1] = 0: reset is active low ? register 0x0d[1] = 1: reset is active high
ad5100 rev. 0 | page 20 of 36 the reset signal is asserted and maintained except when it is triggered by the wdi, which is described in the section. the watchdo g input reset signal is released after the programmable hold time, t rs_hold. as shown in figure 17 , the reset output is push-pull configured with the rail voltage of v 3mon . 05692-017 m1 v 3mon m2 reset figure 17. reset output shutdown warning, shdnwarn an early shutdown warning is available for the system processor to identify the source of failure and take appropriate action before shutting down the external devices. whenever the voltage at v 1mon is detected as overvoltage or undervoltage, or the voltage at v 2mon falls below the threshold, shdnwarn outputs a logic 0. if the processor sees a logic low on this pin, the processor may issue an i 2 c read command to identify the cause of failure reported in the fault detect/status register, at address 0x19. the processor may store the information in external eeprom as a record of failure history. v 4out output v 4out is an open-drain output triggered by v 4mon with a mini- mum propagation delay, t v4out_delay . v 4out can be used as a pwm control over an external device or used as a monitoring signal. most applications using v 4out require disabling of the v 4mon triggered reset function. this function is disabled by writing to register 0x0d[2]. ? register 0x0d[2] = 0: enables v 4mon under threshold to activate reset ? register 0x0d[2] = 1: prevents v 4mon under threshold from activating reset
ad5100 rev. 0 | page 21 of 36 power requirements internal power, v reg the ad5100 internal power, v reg , is derived from v 1mon and becomes active when v 2mon reaches 2.2 v. v 2mon is used to turn ad5100 on and off with a different behavior depending on the v 2mon monitoring mode selection. by default, the ad5100 turns on when the voltage at v 2mon rises above the logic threshold, v 2mon_on . when v 2mon falls below the logic threshold, v 2mon_off , ad5100 turns off 2 seconds after shdn is deasserted. note that ad5100 requires 5 s to start up and that v 1mon must be applied before v 2mon . extension of the ad5100 turn-off allows the system to complete any housekeeping tasks before the system is powered off. shows the default v 2mon and v reg waveforms. figure 19 rising edge triggered wake-up mode if rising edge triggered wake-up v 2mon mode is selected instead, the ad5100 does not turn off when v 2mon returns to a logic low. to configure the part into rising edge triggered mode, set the v 2mon off threshold register, register 0x04[3:1], to 1001. in this mode, once the part is powered on, it can only be powered down by an i 2 c power-down instruction or by removing the supply on the v 1mon pin. to power down the part over the i 2 c bus while in rising edge triggered mode, the user must first ensure that the software power down feature is enabled. ? register 0x18[3] = 0: enable software power-down feature ? register 0x18[3] =1: disable software power-down feature the user must then write to register 0x17[0], to actually power down the ad5100. ? register 0x17[0] = 0: ad5100 not in software power-down ? register 0x17[0] = 1: power down ad5100 this feature is for applications that use a wake-up signal. v otp a 5.5 v supply voltage is needed only during otp fuse program- ming. this voltage should be provided by an external source during factory programming and should have 5.5 v/100 ma driving capability. the otp programming takes a maximum of 12 ms for each register. v otp is not required for normal operation. the v otp has dual functions; it is used for programming the non- volatile memory fuse arrays, as well as serving as a compensation network for internal power stability. as a result, a bypass capacitor must be connected at the v otp pin at all times. a low esr 10 f tantalum capacitor is recommended. ad5100 achieves the otp function through blowing internal fuses. users should always apply the 5.5 v one-time programmable voltage at the first fuse programming attempt. failure to comply with this requirement may lead to a change in the fuse struc- tures, rendering programming inoperable. poor pcb layout introduces parasitic inductance that may affect the fuse programming voltage. therefore, it is mandatory that a 10 f tantalum capacitor be placed as close as possible to the v otp pin. the value and the type of c2 are important. it should provide both a fast response and large supply current handling with minimum supply droop during programming (see figure 18 ). 05692-019 6v to 30v 3v to 30v a pply only 5.5v for otp v 1mon v 2mon v otp ad5100 c2 10f figure 18. power supply requirement 05692-018 v 2mon v 2mon_on* v 2mon,ih t 2sd_hold* t 2sd_hold* t vreg_off_delay t vreg_off_delay t glitch t 2sd_delay* t 2sd_delay* v 2mon_on* v 2mon_off* v 2mon_off* t vreg_on_delay shdn v reg notes 1. 6v < v 1mon < 30v 2. * = programmable t 2sd_delay* figure 19. internal power v reg vs. v 2mon timing diagrams (default)
ad5100 rev. 0 | page 22 of 36 protection for automotive applications, proper external protections on the ad5100 are needed to ensure reliable operation. the v 1mon is likely to be used for battery monitoring. the v 2mon is likely to be used for ignition switch or other critical inputs. as a result, these inputs may need additional protections such as emi, load dump, and esd protections. in addition, battery input requires reverse battery protection and short-circuit fuse protection (see figure 20 ). overcurrent protection if the v 1mon is shorted internally in the ad5100 to gnd, the short-circuit protection kicks in and limits subsequent current to 150 ma in normal operation or 50 ma when the v otp is executed. thermal shutdown when the ad5100 junction temperature is near the junction temperature limit, it automatically shuts down and cuts out the power from v 1mon . the part resumes operation when the device junction temperature returns to normal. esd protection it is common to require a contact rating of 8 kv and a no contact or air rating of 15 kv esd protection for the automotive electronics. as a result, an esd-rated protection device must be used, such as mmbz27vcl, a dual 40 w transient voltage suppressor (tvs) at the v 1mon and v 2mon . load dump protection a load dump is a severe overvoltage surge that occurs when the car battery is being disconnected from a spinning alternator and a resulting long duration, high voltage surge is introduced into the supply line. therefore, external load dump protection is recommended. typically, the load dump overvoltage lasts for a few hundred milliseconds and peaks at around 40 v to 70 v, while current can be as high as 1 a. as a result, a load dump- rated tvs d1 and d2, such as smcj17, are used to handle the surge energy. a series resistor is an inline current limiting resistor; it should be adequate to limit the current without significant drop and yet small enough to not affect the input monitoring accuracy. reverse battery protection reverse battery protection can be provided by a regular diode if the battery monitoring accuracy can be relaxed. otherwise, a 60 v p-channel power mosfet, like the ndt2955, can be used. because of the mosfet internal diode, the battery first conducts through the p1 body diode as soon as the voltage reaches its source terminal. the voltage divider provides adequate gate- to-source voltage to turn on p1, and the voltage drop across the fet is negligible. the resistor divider values are chosen such that the maximum v gs of the p1 is not violated and the current drawn through the battery is only a few microamps. emi protection for emi protection, a ferrite bead or emc rated inductor, such as dr331-7-103, can be used. 05692-020 digipot digipot v 2mon v 1mon d4 smcj17 mmbz27vcl d3 d2 smcj17 d1 r4 2.2 ? r3 2.2 ? vref v reg en r1 2m ? r2 1.5m ? c1 0.1f ndt2955 l1 10h dr331-7-103 f1 c2 0.1f c3 10f ignition switch l1 vmain + ? b+ p1 ad5100 figure 20. protection circuits
ad5100 rev. 0 | page 23 of 36 ad5100 register map table 11 outlines the ad5100 register map, used to configure and control all parameters and functions in the ad5100, and indicates whether registers are writable, readable, or permanently settable. all registers have the same address for read and write operations. the ad5100 ships from its manufacturing factory with default power-up values as listed in the last column. the user can experi- ment with different settings in the various threshold, delay, and configuration registers. once evaluation is complete, the user's own power-up default values can be programmed via a one-time program (otp) feature. when all desired settings have been programmed (or the user is satisfied with the manufacturers defaults), a lock-out bit can be programmed (via otp) to prevent further/erroneous settings from being programmed. the lockout bit is register 0x15[3]. some users may use the ad5100 as a set-and-forget device, that is, program some default values and never need to change these over the life of the application. however, some users may require on-the-fly flexibility, that is, the ability to change settings to values other than those they choose as their defaults. an addi- tional feature of the ad5100 is the ability to temporarily override the otp executed settings and still allow users to program the parts dynamically in the field. all override values revert to otp-executed settings once the ad5100 is power cycled. register writing, reading, otp, and override are explained in the i 2 c serial interface section. table 11. ad5100 register map register address read/ write permanently settable register name and bit description pre-otp power-on default 1 0x01 r/w yes v 1mon overvoltage threshold 0x00 (18.00 v) bit no. description [3:0] four bits used to program v 1mon ov threshold [7:4] reserved 0x02 r/w yes v 1mon undervoltage threshold 0x00 (8.43 v) bit no. description [3:0] four bits used to program v 1mon uv threshold [7:4] reserved 0x03 r/w yes v 2mon turn-on threshold 0x00 (7.47 v) bit no. description [3:0] four bits used to program v 2mon on threshold [7:4] reserved 0x04 r/w yes v 2mon turn-off threshold 0x00 (6.95 v) bit no. description [3:0] four bits used to program v 2mon off threshold [7:4] reserved 0x05 r/w yes v 3mon reset threshold 0x00 (2.93 v) bit no. description [2:0] three bits used to program v 3mon reset threshold [7:3] reserved 0x06 r/w yes v 4mon reset threshold 0x00 (7.54 v) bit no. description [2:0] three bits used to program v 4mon reset threshold [7:3] reserved 0x07 r/w yes v 1mon ov/uv triggered shdn hold (t 1sd_hold ) 0x00 (200 ms) bit no. description [2:0] three bits used to program v 1mon ov/uv triggered shdn hold time [7:3] reserved
ad5100 rev. 0 | page 24 of 36 register address read/ write permanently settable register name and bit description pre-otp power-on default 1 0x08 r/w yes v 1mon ov/uv triggered shdn delay (t 1sd_delay ) 0x00 (1200 ms) bit no. description [2:0] three bits used to program v1mon ov/uv triggered shdn delay time [7:3] reserved 0x09 r/w yes v 2mon turn-on triggered shdn hold (t 2sd_hold ) 0x00 (10 ms) bit no. description [2:0] three bits used to program v 2mon t on triggered shdn hold time [7:3] reserved 0x0a r/w yes v 2mon turn-off triggered shdn delay (t 2sd_delay ) 0x00 (100 ms) bit no. description [2:0] three bits used to program v 2mon t off triggered shdn delay time [7:3] reserved 0x0b r/w yes reset hold (t rs_hold ) 0x00 (200 ms) bit no. description [2:0] three bits used to program reset hold time [7:3] reserved 0x0c r/w yes watchdog timeout (t wd ) 0x00 (1500 ms) bit no. description [2:0] three bits used to program watchdog timeout time [7:3] reserved 0x0d r/w yes reset configuration 0x00 bit no. description [0] 0: reset is active when shdn is active 1: reset is not active when shdn is active [1] 0: reset active low 1: reset active high [2] 0: enables v 4mon under threshold, causing reset 1: prevents v 4mon under threshold from causing reset (for v 4out applications) [3] 0: floating wdi does not activate reset 1: floating wdi activates reset [7:4] reserved 0x0e r/w yes shdn rail voltage configuration 0x00 bit no. description [2:0] reserved [3] 0: shdn rail = v 1mon 1: shdn rail = v reg [7:4] reserved 0x0f r/w yes watchdog mode 0x00 bit no. description [2:0] reserved [3] 0: standard mode 1: advanced mode [7:4] reserved
ad5100 rev. 0 | page 25 of 36 register address read/ write permanently settable register name and bit description pre-otp power-on default 1 0x15 r/w yes program lock (inhib it further programming) 0x00 bit no. description [2:0] reserved [3] 0: further fuse programming allowed 1: further fuse programming disabl ed (note that this bit is otp only) [7:4] reserved 0x16 r/w no special function 1 0x00 bit no. description [0] 0: otp enables 5 a fuse readback sense current 1: otp enables 0.55 a fuse readback sense current [1] 0: otp disables blowing fuses 1: otp enables blowing fuses [2] 0: software assertion of shdn pin is inactive 1: pulls shdn pin low [3] 0: override of permanent settings inactive 1: override of permanent settings active [7:4] reserved 0x17 r/w no special function 2 0x00 bit no. description [0] 0: software power-down of ad5100 inactive 1: software power-down of ad5100 active 2 [7:1] reserved 0x18 r/w no disable special functions 3 0x00 bit no. description [0] 0: allows override of any of the registers in memory except register 0x16 bit[2:0] and register 0x17 bit[0] 1: disables override of any of the registers in memory except register 0x16 bit[2:0] and register 0x17 bit[0] [1] 0: allows otp function 1: disables otp function [2] reserved [3] 0: allows software power-down function 1: disables software power-down function [4] 0: allows software assertion of shdn pin 1: disables software assertion of shdn pin [7:5] reserved
ad5100 rev. 0 | page 26 of 36 register address read/ write permanently settable register name and bit description pre-otp power-on default 1 0x19 read- only no fault detect and status (bits[3:0] are level triggered bits th at indicate the current state of the comparators monitoring the v 1mon and v 2mon input pins; bits[6:4] are edge triggered fault detection bits that indica te what error conditions were present when a shdn event occurred) 0x40 bit no. description [0] 1 = v 2mon input < v 2mon off threshold [1] 1 = v 2mon input > v 2mon on threshold [2] 1 = v 1mon input < v 1mon uv threshold [3] 1 = v 1mon input > v 1mon ov threshold [6:4] 000: none 001: v 1mon uv only 010: v 1mon ov only 011: never occurred 100: v 2mon below off only (default) 101: v 1mon uv and v 2mon below off both occurred 110: v 1mon ov and v 2mon below off both occurred 111: never occurred [7] reserved 1 default settings of ad5100 when sh ipped from manufac turers factory. 2 v 2mon must be 0 v (that is, v 2mon must be configured in edge sensitive mode) for software power-down. 3 these register bits are set on ly. to clear them, the ad5100 must be power cycled. in some cases, the ad5100 can be connected t o an i 2 c bus with lots of activity. setting these bits is an added means of ensuring that any errone ous activity on the bus does not cause ad5100 special functions to become active.
ad5100 rev. 0 | page 27 of 36 i 2 c serial interface control of the ad5100 is accomplished via an i 2 c-compatible serial bus. the ad5100 is connected to this bus as a slave device (the ad5100 has no master capabilities). the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which occurs when sda goes from high to low while scl is high. the following byte is the slave address byte, which consists of the 7-bit slave address followed by an r/ w bit that determines whether data is read from or written to the slave device 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condi- tion. in the read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse and high during the 10 th clock pulse to establish a stop condition. for the ad5100, write operations contain either one or two bytes, while read operations contain one byte. the ad5100 makes use of an address pointer register. this address pointer sets up one of the other registers for the second byte of the write operation or for a subsequent read operation. table 12 shows the structure of the address pointer register. bits [6:0] signify the address of the register that is to be written to or read from. bit 7 is used when otp mode is invoked (use of this bit is explained in the one-time programmable (otp) options section) and should be 0 for normal write/read operations. table 12. address pointer register structure bit number function 7 otp enable 6 address bit 6 5 address bit 5 4 address bit 4 3 address bit 3 2 address bit 2 1 address bit 1 0 address bit 0 (lsb) scl the serial input register clock pin shifts in one bit at a time on positive clock edges. an external 2.2 k to 10 k pull-up resistor is needed. the pull-up resistor should be tied to v 3mon , provided v 3mon is sub-5 v. sda the serial data input/output pin shifts in one bit at a time on positive clock edges, with the msb loaded first. an external 2.2 k to 10 k pull-up resistor is needed. the pull-up resistor should be tied to v 3mon , provided v 3mon is sub-5 v. ad0 the ad5100 has a 7-bit slave address. the six msbs are 010111, and the lsb is determined by the state of the ad0 pin. when the i 2 c slave address pin, ad0, is low, the 7-bit ad5100 slave address is 0101110. when ad0 is high, the 7-bit ad5100 slave address is 0101111 (pulled up to 3.3 v maximum). the ad0 pin allows the user to connect two ad5100 devices to the same i 2 c bus . tabl e 13 and figure 21 show an example of two ad5100 devices operating on the same serial bus independently. table 13. slave address decoding scheme ad0 programming bit ad0 device pin device addressed 0 0 v 0x2e (u1) 1 3.3 v max 0x2f (u2) 05692-021 scl sda 5v rp rp sda ad0 scl ad5100 u2 5v sda ad0 scl ad5100 u1 master 3.3v max figure 21. two ad5100 devices on one bus
ad5100 rev. 0 | page 28 of 36 writing data to ad5100 when writing data to the ad5100, the user begins by writing an address byte followed by the r/ w bit set to 0. the ad5100 acknowledges (if the correct address byte is used) by pulling the sda line low during the ninth clock pulse. the user then follows with two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second byte is the data to be written to the internal data register. after each byte, the ad5100 acknowledges by pulling the sda line low during the ninth clock pulse. illustrates this operation. figure 22 reading data from ad5100 when reading data from an ad5100 register, there are two possibilities. ? if the ad5100 address pointer register value is unknown or not at the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. this is done by performing a write to the ad5100, but only a value containing the register address is sent because data is not to be written to the register. this is shown in figure 23 . a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte from the data register. this is shown in . figure 24 ? if the address pointer is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register. table 14 shows the readback data byte structure. bits[6:0] contain the data from the register just read. bit 7 only has significance when otp mode is being used, and should be ignored for normal read operations. the majority of ad5100 registers are four bits wide, with only the fault detect and status register and disable special functions register at seven bits and five bits wide, respectively. table 14. readback data byte structure bit number function 7 otp okay 6 d6 5 d5 4 d4 3 d3 2 d2 1 d1 0 d0 (lsb) 0 5692-022 sda frame 1 slave address byte frame 2 address pointer byte frame 3 data byte scl ack. by ad5100 ack. by ad5100 ack. by ad5100 stop by master start by master 01 0 11 1 ad0 r/w otp ap6 ap5 ap4 ap3 ap2 ap1 ap0 d7 d6 d5 d4 d3 d2 d1 d0 figure 22. writing a register address to the address pointe r register, then writing data to the selected register 0 5692-023 sda frame 1 slave address byte frame 2 address pointer byte scl ack. by ad5100 ack. by ad5100 stop by master start by master 01 0 11 1 ad0 r/w otp ap6 ap5 ap4 ap3 ap2 ap1 ap0 figure 23. dummy write to set proper address pointer 0 5692-024 sda frame 1 slave address byte frame 2 read data byte scl ack. by ad5100 no ack. by master stop by master start by master 01 0 11 1 ad0 r/w otp ok d6 d5 d4 d3 d2 d1 d0 figure 24. read data from the address pointer register
ad5100 rev. 0 | page 29 of 36 permanent setting of ad5100 registers (otp function) when the user wants to permanently program settings to the ad5100, the one-time program (otp) function is invoked (note the requirements for the capacitor on the v otp pin in the power requirements section). to complete a permanent program cycle for a particular register, the following sequence should be used: 1. set bit 0 = 1 in register 0x16 using a normal write operation. 2. set bit 1 = 1 in register 0x16 using a normal write operation. 3. apply a 5.5 v (100 ma) voltage source to the otp pin. this provides the current for the programming cycle. 4. write the desired permanent data to the register of choice, using a write operation with the otp bit set to 1 in the address pointer byte. 5. wait a period of 12 ms for the ad5100 to perform the permanent setting of the internal register. the user has the opportunity to check whether the ad5100 is programmed correctly by performing a read instruction with the otp bit set to 1 in the address pointer byte (for example, set the address pointer to 0x81 to check v 1mon-ov ) and monitoring the state of bit 7 (otp okay) in the read back data byte. ? otp okay = 1 indicates that the ad5100 is programmed correctly ? otp okay = 0 indicates that the ad5100 is programmed incorrectly note that read back of the otp okay bit is available only for the read cycle following immediately after the program cycle. if a write or read of a different register is done immediately after the program cycle, the opportunity for verifying whether the programming was successful will have been missed. figure 25 shows the recommended way of executing a program, then reading back and verifying the v 1mon overvoltage threshold register (assuming that step 1 to step 3 have already been completed). when all default registers have been programmed, the lock bit should be set. user-programmed defaults do not become active until the lock bit is programmed. programming the lock bit is done in exactly the same manner as all other registers in table 11 . the lock bit is register 0x15, bit 3. temporary override of default settings even with the lock bit set, it is possible to temporarily override the default values of any of the permanently programmable registers. to override a permanent setting in a particular register (when the lock bit is programmed), the following sequence should be used: 1. set bit 3 = 1 in register 0x16 (special function 1). 2. write the desired temporary data to the register of choice. while the override bit (bit 3) is set in register 0x16, the user can override any registers by simply writing to them with new data. to reset an overridden register to its default setting, the following sequence should be used: 1. set bit 3 = 0 in register 0x16. 2. write a dummy byte to the register of choice. clearing the override bit in register 0x16 does not cause all overridden registers to revert to their defaults at the same time. for example, imagine that the user overrides register 0x01, register 0x02, and register 0x03. if the user subsequently clears the override bit in register 0x16 and writes a dummy byte to register 0x01, register 0x01 reverts to its default value. how- ever, register 0x02 and register 0x03 still contain their override data. to revert both registers to their default values, the user must write dummy data to each register individually. power cycling the ad5100 also resets all registers to their programmed defaults. 010111ad0 s device address w ack 0x81 ack 0x0f ack p set addr pointer to v 1mon ovthres otp bit =1 set v 1mon ov threshold = 13.2v 12ms delay 010111ad0 s device address r ack ack 0x81 0x8f nack p set addr pointer to v 1mon ov thres otp bit =1 confirmed v 1mon ov threshold = 13.2v output from master output from ad5100 s = start bit p = stop bit ack =acknowledge nack = no acknowledge r = read w = write 05692-125 figure 25. setting and validating otp register setting
ad5100 rev. 0 | page 30 of 36 applications information car battery and infotainment system supply monitoring the ad5100 has two high voltage monitoring inputs with shut- down and reset controls over external devices. for example, the v 1mon and v 2mon can be used to monitor the signals from a car battery and an ignition key in an automobile, respectively (see figure 26 ). the shutdown output can be connected to the shutdown pin of an external regulator to prevent false condi- tions such as a weak battery or overcharging of a battery by an alternator. the reset output can be used to reset the processor in the event of a hardware or software malfunction. an example of the input and output responses of this circuit is shown in figure 27 .
ad5100 rev. 0 | page 31 of 36 05692-025 digipot digipot digipot v 4mon v 3mon digipot fd fd 1 2 c shdn fd v reg v 2mon v 1mon d4 smcj17 mmbz27vcl d3 d2 smcj17 d1 r4 2.2 ? r3 2.2 ? vref v reg en osc r1 2m ? r2 1.5m ? c1 0.1f ndt2955 l1 10h dr331-7-103 f1 c2 0.1f c3 10f ignition switch l1 vmain +? b+ p1 ov uv off on v 3mon shutdown controller and adjustable shdn hold and delay reset generator and adjustable reset hold driver programmable driver load deselect 1 3 2 reset generator programmable watchdog otp fuse array memory map fd register (fault detection) 4 times i 2 c controller set configurations program parameters read status i 2 c shdn shdnwarn v 4out reset pa vcc dac vout gnd vin vout v reg2 sd gnd vin +3.3 +5v v reg1 sd vdd dvdd 1.8v 3.3v i/o i/o dsp/ microprocessor in out codec signal reset r2 scl sda ad0 r3 c3 0.1f c2 10f wdi votp mr v 3mon dac ad5100 shdn figure 26. typical dsp in car infotainment application
ad5100 rev. 0 | page 32 of 36 05692-026 battery ov uv ignition v reg < t glitch 5v 3.3v wdi high-z +5v brownout reset wdi reset wdi reset v 2mon off shutdown shutdown enable reset mr reset shdn mr reset t vreg_off_delay t vreg_on_delay microprocessor failed reset high-z uv shutdown shutdown enable reset microprocessor failed shutdown figure 27. example of shdn and reset responses of circuit shown in figure 26
ad5100 rev. 0 | page 33 of 36 battery monitoring with fan control v 4mon can be used with v 4out in tandem to form a simple pwm control circuit. for example, as shown in figure 28 , when a temperature sensor output connects to the v 4mon input, with the proper threshold level set, v 4out outputs high whenever the temperature goes above the threshold. this turns on the fet switch, which activates the fan. when v temp drops below the threshold, v 4out decreases, which turns off the fan. battery state of charge indicator and shutdown early wa rning monitoring in the automotive application, the system designer may set the battery threshold to the lowest level to allow an automobile to start at the worst-case condition. if the battery remains at the low voltage level, it is indeed a poor battery. however, there is no way to warn the driver. as a result, the system designer can use v 4out as the battery warning indicator. by stepping down the battery voltage monitored at v 4mon , the led is lit, which gives a battery replacement warning. the circuit is shown in figure 30 . 05692-027 ad5100 v 2mon v 3mon v 4mon mr wdi sda scl v 1mon v 4out shdnwarn shdn reset wdi mr battery ignition v reg v temp mr wdi clk v reg v reg battery sd microprocessor clk miso/mosi pa tmp35 vtemp figure 28. power amp moni toring and fan control 05692-028 v temp v 4out notes 1. v 4mon reset disabled. v 4mon threshold figure 29. v 4out with respect to v temp , with v 4mon reset disabled in circuit shown in figure 28 05692-029 ad5100 v 4mon sda scl v 4out shdnwarn shdn v 1mon battery v 2mon ignition clk microprocessor clk miso/mosi figure 30. battery state of charge indication
ad5100 rev. 0 | page 34 of 36 rising edge triggered wake-up mode as indicated in figure 31 , the microprocessor can control its own power-down sequence using the rising edge triggered wake-up signal. the operator must select the rising edge triggered wake-up mode setting for the v 2mon turn-off threshold value, as shown in table 6 , by setting register 0x04[3:1] = 1001. when the rising edge wake-up signal is detected by v 2mon , the ad5100 is powered up with the shdn pin pulled high. the external regulator is turned on to supply power to the microprocessor. a reset pulse train is generated at the reset output if there is no watchdog activity. the pulse continues until the correct watchdog signal appears at the ad5100 wdi pin. the shutdown pin remains high as long as the ad5100 continues to receive the correct watchdog signal. when the microprocessor finishes its housekeeping tasks or powers down the software routine, it stops sending a watchdog signal. in response, the ad5100 generates a reset. the shut- down pin is pulled low 2 seconds after, and the regulator output drops to 0 v, which shuts down the microprocessor. at that point, the ad5100 enters sleep mode. 05692-030 ad5100 v 2mon wdi sda scl v 1mon shdn reset battery can wake up pulse(s) v reg v i v o sd microprocessor v dd i/o rs i/o i/o figure 31. rising edge triggered wa ke-up mode 05692-031 scl notes 1. 6v < v 1mon < 30v. 2 . select v 2mon _ off = rising edge trigger/can wake up mode. sda write v 2mon wdi scl sda reset shdn figure 32. rising edge triggered operation of circuit shown in figure 31
ad5100 rev. 0 | page 35 of 36 outline dimensions compliant to jedec standards mo-137-ab 012808-a controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 16 9 8 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) figure 33. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches ordering guide model temperature range package descriptio n package option ordering quantity AD5100YRQZ-rl7 1 ?40c to +125c 16-lead qsop rq-16 1,000 AD5100YRQZ 1 ?40c to +125c 16-lead qsop rq-16 9,800 1 z = rohs compliant part.
ad5100 rev. 0 | page 36 of 36 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05692-0-9/08(0)

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